A Hardware-Aware Edge-Constrained Region Verification Network for Two-Stage UAV Detection
2026 34th Signal Processing and Communications Applications Conference (SIU), İstanbul, Türkiye, 7 - 10 Temmuz 2026, ss.1-4, (Tam Metin Bildiri)
- Yayın Türü: Bildiri / Tam Metin Bildiri
- Doi Numarası: 10.1109/siu71813.2026.11636375
- Basıldığı Şehir: İstanbul
- Basıldığı Ülke: Türkiye
- Sayfa Sayıları: ss.1-4
- Açık Arşiv Koleksiyonu: AVESİS Açık Erişim Koleksiyonu
- Ankara Yıldırım Beyazıt Üniversitesi Adresli: Evet
Özet
Autonomous detection of Low-Slow-Small UAVs on edge devices necessitates two-stage pipelines due to memory bandwidth constraints. However, forcing general-purpose full-frame detectors into region of interest verification tasks yields sub-optimal results. In this study, it is empirically demonstrated that edge-constrained verification is not merely a scaled-down detection problem, and the hardware-aware EMA-Det architecture is proposed as a system demonstrator. Equipped with Laplacian kernel initialization and dynamic early-exit mechanisms, the model empirically shows that global pooling-based attention modules degrade target features at constrained resolutions. Under fair comparison at 128x128 input, pre-trained YOLOv8n in verification-mode achieved 88.7 percent recall, while EMA-Det reached 99.2 percent recall with 10 times fewer operations and 3 times lower peak activation memory.