Fault tolerance for multi-threaded applications by leveraging hardware transactional memory
2013 ACM International Conference on Computing Frontiers, CF 2013, Ischia, İtalya, 14 - 16 Mayıs 2013, (Tam Metin Bildiri)
- Yayın Türü: Bildiri / Tam Metin Bildiri
- Doi Numarası: 10.1145/2482767.2482773
- Basıldığı Şehir: Ischia
- Basıldığı Ülke: İtalya
- Anahtar Kelimeler: Error detection, Error recovery, HTM, Redundancy
- Ankara Yıldırım Beyazıt Üniversitesi Adresli: Hayır
Özet
Providing fault tolerance especially to mission critical applications in order to detect transient and permanent faults and to recover from them is one of the main necessity for processor designers. However, fault tolerance for multi-threaded applications presents high performance degradations due to comparing the results of the instruction streams, checkpointing the entire system and recovering from the detected errors to an agreed state. In this study, we present FaulTM-multi, a fault tolerance scheme for multi threaded applications running on transactional memory hardware which reduces these performance degradations. FaulTM-multi decreases the performance degradation of lockstepping, a conventional fault detection scheme, from 23% and 9% to 10% and 2% for lock-based parallel and TM applications respectively. Also, FaulTM-multi creates 28% less checkpoints compared to Rebound, the state of the art checkpointing scheme. Copyright 2013 ACM.