FPGA Implementation of AWGN Noise Generator Using Box-Muller Method

Caglan A., Inceoz E., Balcisoy E., Ozbek M. E., ÇAVUŞ E.

24th Signal Processing and Communication Application Conference (SIU), Zonguldak, Turkey, 16 - 19 May 2016, pp.1813-1816 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/siu.2016.7496114
  • City: Zonguldak
  • Country: Turkey
  • Page Numbers: pp.1813-1816
  • Ankara Yıldırım Beyazıt University Affiliated: Yes


In this study, AWGN generator is implemented on FPGA by using Box-Muller method. Firstly, AWGN generator is designed with floating point in C++ language. Then fixed-point model is developed in C++. The means and stardard deviations of the designs with fixed point and floating point are tested and it is proved that designs have normal distribution. After this step, the fixed-point design is modelled in Verilog HDL. The design in Verilog HDL is matched with C++ model and then the Verilog HDL model is implemented on the Xilinx Virtex-7 FPGA. The design implemented on FPGA has 110 MHz clock frequency, and 7.04 Gbps data speed. The AWGN generator designed in C++ has 39 Mbps data speed and it is confirmed that the AWGN generator implemented on FGPA is working 200 times faster than C++ model.