Analysis and FPGA Implementation of Zero-Forcing Receive Beamforming with Signal Space Diversity under Different Interleaving Techniques

Reşat M. A., Çiçek A., Özyurt S., Çavuş E.

Journal of Circuits, Systems and Computers, vol.29, no.1, 2020 (SCI-Expanded) identifier

  • Publication Type: Article / Article
  • Volume: 29 Issue: 1
  • Publication Date: 2020
  • Doi Number: 10.1142/s0218126620500073
  • Journal Name: Journal of Circuits, Systems and Computers
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Academic Search Premier, Applied Science & Technology Source, Compendex, Computer & Applied Sciences, INSPEC
  • Keywords: field-programmable gate array, multiple-input multiple-output, Signal space diversity, spatial interleaving, time interleaving, zero-forcing receive beamforming
  • Ankara Yıldırım Beyazıt University Affiliated: Yes

Abstract

We combine multiple-input multiple-output zero-forcing receive beamforming (ZFRBF) with time and spatial component interleaved signal space diversity (SSD) and analyze the system's error performance and implementation complexity. A transreceiver system with two transmit and M (M≥2) receive antennas is considered where the number of simultaneous substreams equals two. The error performance of the proposed scheme with binary phase-shift keying (BPSK) and quadrature phase-shift keying (QPSK) modulations is studied. Under the time component interleaved SSD case, we derive an exact average bit error probability expression for BPSK and a tight approximation on the average symbol error probability for QPSK. The signal constellation rotation angles are accordingly computed. Using a similar approach, the signal constellation rotation angles are also determined for the scenario of spatial component interleaved SSD. It is demonstrated that the performance of the original ZFRBF model can be improved significantly by utilizing SSD especially with the time interleaving method. Another contribution to the literature is to study hardware complexity of the proposed scheme on FPGA. It is shown that while achieving considerable performance gain, SSD introduces only an insignificant increase to the system complexity without any extra bandwidth or time slot usage.